This article takes the bank's existing queuing system as an example, and proposes the interface design of the single-chip queuing system of the IIC bus. Through the simulation test of the system, it not only simplifies the design circuit, reduces the circuit board area, saves the components and parts in the conventional design, and reduces the use Various expenses, and system energy consumption, noise reduction, reliability and other performance have been improved. In MCS-51 series single-chip microcomputers without IIC bus interface data measurement and control and intelligent instrumentation instruments, you can increase the system interface device type through IIC bus , Reduce system cost, improve application system performance [1-3].
1 IIC bus
The IIC bus (Inter Integrate Circuit Bus) is a bidirectional two-wire bus composed of a serial clock line (SCL) and a serial data line (SDA). It connects different devices with IIC bus through two wires Data is transferred between devices, and the data transmission rate can reach up to 3.4 Mb / s in high-speed mode, which simplifies circuit design and improves the efficiency of hardware use, making IIC bus widely used in serial transmission design of embedded systems. In the central control center, audio integrated circuit and video and other digital control systems.
1.1 IIC bus timing
(1) Start and stop
When the bus is not busy, the clock and data lines remain high. The start condition (S) is when the clock line is at a high level and the data line is a falling edge, and the stop condition (P) is when the clock line is at a high level and the data line is a rising edge. .
(2) Data transmission
The transmission of a data bit requires a clock pulse, and a flag bit is added after every 1 B. When the flag bit generated by the transmitter is at a high level, the master device generates an additional flag bit clock pulse. The information on the data line SDA should only keep the data stable when the clock pulse is high, otherwise the data on the data line SDA will become a control signal, as shown in Figure 2.
(3) IIC bus protocol
Before transmitting data on the IIC bus, the received device address should be marked first. When the IIC bus is started, this address and the first transmitted byte are transferred together.
In this system, the PCF8563 chip acts as a slave transmitter or slave receiver. The SCL signal line is only the input line, and the SDA data line is a bidirectional signal line.
1.2 Overview of chip PCF8563
PCF8563 is a classic low-power real-time clock / calendar chip [4], with IIC bus interface technology, the maximum transmission speed of the bus can reach 400 kb / s, after each write and read data, the internal word address register will automatically increase It has the characteristics of low power consumption and high precision. PCF8563 has timer function, multiple alarm functions, interrupt output function and clock output function. It can complete a variety of timing services. It can also implement watchdog technology for single-chip systems. Its internal oscillation circuit, clock circuit, low voltage 1.0 V The detection circuit and IIC two-wire bus communication method have solved the 2000 problem at the same time, which not only makes the peripheral circuit and its simplicity, but also increases the reliability of the chip. It can be widely used in water meters, electricity meters, mobile phones, portable instruments, fax machines , Battery power and other products.
2 System design
2.1 Analysis of system requirements
There are 8 business service windows in the bank service lobby. The service window attributes are divided into five types of service business descriptions, which can be used for personal wealth management business, corporate business, VIP bank card business, personal deposit and withdrawal and mobile phone bill collection, water and electricity. Fee and other mixed services.
Performance requirements of the queuing system: queuing machines are placed at the entrance of the service hall for the depositor to request the queuing number in chronological order and print the number; the personnel in the service window can call the number through the button; after the number is called, the number is displayed on the screen and the speaker is used for two consecutive Secondary play number information; the staff can make related settings (functions, modes, menus, etc.) of the queuing system through the background.
2.2 System hardware design
SCM queuing system is composed of bank counter operation module, memory module, counter calling number module, liquid crystal display module, and depositor operation module. The system structure is shown in Figure 3. The IIC circuit in the system is used for the application of interface such as parameter memory (E2PROM) and real-time accurate clock [2].
The real-time accurate clock uses a low-power CMOS real-time calendar / clock chip, through a frequency divider (used to provide the source clock to the real-time clock RTC), timer, programmable clock output, power-down detector, alarm and IIC bus Interface to set the precise clock signal necessary for the system. All data and addresses are serially transmitted through the IIC bus interface. After each write and read of data, the word address register will automatically increment [5].
The parameter memory (E2PROM) [6] uses a low-power CMOS serial IIC circuit to record counter operations and depositor queuing and other information through the on-chip storage space. Its operation control completely follows the IIC protocol.
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