The at91sam9263 embeds an ARM926EJ-S microcontroller (MCU) based on 200 MIPS (million instructions per second), which solves the need for graphical interfaces, data-intensive applications such as networked medical monitoring devices and GPS navigation systems. Bottlenecks encountered by traditional microcontrollers based on ARM9.
The at91sam9263 uses 27 DMA (Direct Memory Access) channels, including Atmel 18-channel PDC (Peripheral Direct Memory Access Controller), a 9-layer bus matrix, and data/indication TCM (tightly coupled memory). Two other buses to enhance CPU performance and provide on-chip data transfer rates of up to 41.6 Gbps. Two EBIs (External Bus Interfaces) support more than one billion bytes of external memory.
Human machine interface. The on-chip human-machine interface peripherals include a camera interface, TFT/STN LCD controller, a 6-channel audio front-end interface (AC97), I2S, and a 2D graphics coprocessor that reduces CPU line and block transfer. , polygon fill and editing capabilities.
Networking and communication. Networked peripherals include a 12Mbps USB host and device, 10/100 Ethernet MAC (Ethernet Media Access Controller), and 1 Mbps CAN (Controller Area Network). There are also four USART (Universal Synchronous/Asynchronous Transceiver), two 50 Mbps SPI (Synchronous Parallel Interface), CompactFlash, SDIO (MCI) and one TWI (Two-Wire Interface) that can be connected to a GPRS modem such as GPRS And wired and wireless communication modules such as Wi-Fi.
The peripheral DMA controller allows data transfer from peripherals to memory without the need for a CPU - a traditional ARM9-based processor implements a byte between memory and peripherals by issuing a load-store indication (requiring at least 80 CPU cycles) The transmission of data. These processors operate at 200 MHz (bus frequency 100 MHz), and even when the memory management unit and the indicator/data cache controller are activated, they typically reach their functional limits when the transmission reaches approximately 20 Mbps.
Atmel's at91sam9263 integrates 18 simple, silicon-efficient, single-cycle peripheral PDCs, five DMA controllers (with burst mode support for USB hosts), Ethernet MAC, camera interface, LCD controller, 2D graphics controller, and a memory-to-memory DMA controller (supports burst mode, decentralized aggregation, and linked lists). The DMA controller completely relieves the data transfer burden between the external serial port and the memory. At a transmission speed of 20 Mbps, Atmel's SAM9263 still has 88% MIPS available for application execution.
The 11-layer bus and 96 kilobytes of on-chip SRAM (static memory) eliminate bandwidth bottlenecks. Atmel has configured 11 buses and 96 kilobytes of on-chip scratchpad SRAM on the AT92SAM9263. The SRAM can be partially configured as tightly coupled data and indicator memory. These buses provide multiple parallel on-chip transmission channels and a total on-chip bandwidth of 41.6 Gbps.
Two EBIs allow the ARM9 CPU and graphics processor to work simultaneously and in parallel. At91sam9263 has two EBIs: one is the system memory interface and the other is the human machine interface. The second interface eliminates the need for the LCD controller and CPU to share memory while increasing the available CPU MIPS by 20% to 40%.
[at91sam9263 chip resources]
1. A processor that combines ARM926EJ-STM ARM THUMB
-DSP instruction extension, JAZELLE technology for JAVA acceleration processor
-16K byte cache, 16K byte instruction cache, write buffer
- at 220MHZ 220MIPS
-Memory Management Unit
-EmbededICETM, debug communication channel support
- Medium-scale execution of embedded macrocell structures
2, bus matrix
-9 32-bit layer matrices, allowing on-chip bus bandwidth up to 28.8Gbps
- Boot mode option, image command
3, embedded memory
- One 128K byte internal ROM for single cycle access at maximum bus matrix speed
- One 80K byte internal SRAM for single cycle access at maximum processor speed or maximum bus matrix speed
- One 16K byte internal SRAM for single cycle access at maximum bus matrix speed
4, dual external bus interface (EBI0-EBI1)
-EBI0 supports SDRAM, static memory, ECC Nand Flash and Compact Flash enabled.
-EBI1 supports SDRAM, static memory, ECC Nand Flash enabled.
5, DMA controller
- Act as a bus matrix master
- Embed two unidirectional channels with programming priority, address generation, channel buffering and control.
6, 20 peripheral DMA controller channels
7, LCD controller
- Support active or passive display
- Each pixel can be up to 24 bits in TFT mode, and up to 16 bits per pixel in STN color mode.
- Up to 16M color in TFT mode, resolution up to 2048X2048, support for virtual screen cache.
8, 2D graphics accelerator
- Line drag, block shift, polygon fill, cut, command queuing.
9, camera sensor interface
- ITU-R BT.601/656 external interface, programmable frame capture rate.
The -12bit interface supports high sensitivity sensors.
-SAV and EAV synchronization, preview path with scaler, YcbCr format.
L0, USB2.0 full speed (12Mbit/s) host dual port
- Dual on-chip transceiver
- Integrated FIFO and dedicated DMA channel.
L1, USB2.0 full speed (12Mbit/s) device port
- On-chip transceiver with 2,432 bytes of configurable integrated DPRAM.
L2, 10/100 Base-T Ethernet MAC
- Independent media interface or simplified independent media interface.
- There are 28 byte FIFOs and dedicated DMA channels for receiving and transmitting.
L3, all features of the system controller, including
- Reset the controller and stop the controller.
-20 32-bit battery backup registers for a total of 80 bytes.
- Clock generator and power management controller.
Advanced interrupt controller and debug unit.
A timer during the week, a watchdog timer and a dual real time timer.
1) Reset controller (RSTC)
- Based on two power-on reset units, reset source identification and reset output control.
2) Stop controller (SHDWC)
- Programmable pin control and wake-up circuitry.
3) Clock Generator (CKGR)
The -32768Hz low power oscillator is used in the backup power supply to provide a permanent low speed clock.
-3-20MHz on-chip oscillator, two maximum 240MHz PLLs.
4) Power Management Controller (PMC)
- Lower clock operation mode, software programmable power supply optimized capacity.
- 4 programmable external clock signals.
5) Advanced Interrupt Controller (AIC)
- Individually shieldable, 8-level priority, vector interrupt source.
- Two external interrupt sources and one fast interrupt source, false interrupt protection.
6) Debug unit (DBGU)
- 2-wire UART and support debug communication channel, programmable ICE access blocking.
7) Periodic interval timer (PIT)
-20bit interval timer plus 12bit interval counter.
8) Watchdog Timer (WDT)
- Encryption protection, one-time programming only, windowed 16-bit counter running on low clock
9) Two real-time timers (RTT)
- Free backup counter with 16-bit prescaler running on low clock
L4, 5 32-bit parallel input/output controllers (PIOA, PIOB, PIOC, PIOD and PIOE)
-160 programmable I/O lines are simultaneously transmitted to external devices 2 I/O
- Signal input, change, and interrupt performance for each I/O line
- Individually programmable open-drain output, pull-up resistor, synchronous output
-16 fully programmable information target mailbox, timestamp counter
L5, two multimedia interface cards (MCI)
– SD card / SDIO and MulTIMediaCard driver
– Automation protocol control and rapid automated data transfer with PDC
– Two SD card slot support per controller
L6, two synchronous serial controllers (SSC)
– each receiver and converter has separate clock and frame sync signals
– I2S analog interface support, time zone synchronous transfer support
– High-speed continuous data stream performance with 32-bit data converters
L7, an AC97 controller (AC97C)
– 6-channel signal AC97 analog front-end interface, slot assignment
L8, 3 universal synchronous and asynchronous transceivers (USART)
– Independent baud rate generator, IrDA infrared modulation, demodulation, Manchester encoding, decoding
– Support ISO7816 T0/T1 smart card, hardware handshake signal, RS485 support
L9, two master-slave serial bus interfaces (SPI)
– 8 to 16-bit programmable data length, 4 external bus chip options
– Synchronous communication at 90 Mbits per second
20, a 3-channel 16-bit timer and counter (TC)
– Three external clock inputs with 2 multi-function I/O jacks per channel
– Dual PWM generator, schematic capture, waveform capture mode, connection, disconnection performance
2l, a four-channel 16-bit PWM controller WMC)
22, a two-wire interface (TWI)
– Main mode support, support for all Atmel EEPROMs
23. IEEE 1149.1 JTAG boundary scan for all digital pins
24, power supply
–VDDCORE and VDDBU voltages are 1.08V to 1.32V
–VDDOSC and VDDPLL voltages are 3.0V to 3.6V
–VDDIOP0 (peripheral I/Os) voltage is 2.7V to 3.6V
–VDDIOP (Peripheral I/Os) voltage is 11.65V to 3.6V
–VDDIOM0/VDDIOM1 programmable voltage is 1.65V to 1.95V or 3.0V to 3.6V (memory I/Os)
At91sam9263 CAN driver debugging experience
Before debugging the CAN device, it is generally a USB to CAN debugging tool bought from Taobao. The 100K-800K baud rate basically has no problem, and we have not considered too many details. One day, a customer said that our CAN driver has a problem, and they can't communicate with their CAN debugging device. Do not hesitate to use the tool to go to it, try it. . . .
é‚ By using its CAN debugging tool, I haven’t checked it for ZLG’s products for a long time. I met Zhou Ligong's big bull, CAN expert, claiming that there is no CAN problem that he can't solve. It turns out that it is expected that Zhou Ligong's CAN analyzer is a group of people who got it. Now, don't do research and development, change to do Service. Take the Can analyzer to find out that the CAN waveform baud rate sent by our CPU is not good, although it is set to 500K, but because the CPU clock frequency is unconventional frequency, after the frequency division, the CAN clock is about 512K, ZLG's CAN The debugging tools are standard products. They generally require strict timing, so the communication between our equipment and its debugging tools is not available, but the USB to CAN debugging tools purchased online will set the SJW domain to be larger. Or about 4, can communicate with most of the CAN, even if the other party's CAN baud rate is not accurate, there is a large error.
The vast majority of CAN problems should be based on the accuracy of the baud rate, but in general there is no such accurate test instrument, so everyone is confused. Properly adjusting the size of the SJW sync jump width can solve this problem to a certain extent, but it is not the best solution. Although the phenomenon is seen, oh, the communication is normal, the package I sent can be received by the other party, and the data packet sent by the other party can also be received. However, the fact is that there are many retransmissions here, benefiting from CAN protocol, retransmission, response, etc.
The following is a brief description of the analysis of CAN baud rate.
For example, 500K baud rate, one bit is divided into 16 time factors
500K * 16 = 8M
So the CAN clock should try to make a multiple of 8M. The error is as small as possible.
Similarly, the corresponding relationship between other baud rates and clocks is estimated.
In our 9263 application, MCLK = PLLA/2, the CAN clock is divided from MCLK.
Therefore, the value of PLLA should be an integer multiple of 16M. Our PLLA is generally set to 200M---150M, so PLLA can take 192M 176M 160M and so on.
The setting under WinCE is relatively simple. After Eboot is started, the space can enter the eboot configuration menu. You can directly set the CPU's main frequency and frequency division, not to go into details.
The streaking program needs to set the multiplier and the crossover coefficient by itself. The PLL calculation tool is downloaded from the ATMEL official website. It is not very helpful, but it may not be as accurate, but it is as close as possible.
#define BOARD_MCK ((16367660 * 98 / 10) / 2) /*160M*/
Set to 160M as above
In addition to the modification of this macro definition, some changes need to be made in board_lowlevel.c.
#define BOARD_MULA (AT91C_CKGR_MULA & (97 "16))
#define BOARD_DIVA (AT91C_CKGR_DIVA & 10)
That is the two coefficients, pay attention to the frequency division coefficient unchanged, but the multiplication factor is reduced by one, the reason is clear in the data sheet.
I thought it would be fine, but there is still a place to ignore, look at the code.
Void LowLevelInit( void ) function
Void LowLevelInit( void )
{
....
#if ! Defined(sdram)
/* IniTIalize main oscillator
Initialize the main oscillator, clock, etc.
#endif //#if ! Defined(sdram)
. . . . . . . . . . .
}
The whole process is included in the judgment of the sdram macro. If sdram is defined, the following processing is not performed. Well, how can you not do this processing? Explain the above two macro definitions.
This macro definition is not defined in the file, but in the compiler's project settings.
OpTIons-Ã C/C++ Compiler Preprocessor tab, bottom=Defined symbols
You can also remove sdram directly.
Has the entanglement of SDRAM initialization been carried out somewhere?
Debugging questions about SPI startup
What is the problem? The quality of SPI DATA FLASH itself is caused by problems.
The phenomenon reflected is that there is no problem reading data from the 0 address of SPI DATAFLASH, but if you read data from any middle section, there is a serious address offset problem.
The debugging process and steps are as follows:
Originally thought that the CPU (AT91SAM9263 has A version and B version) version has a problem, resulting in the inability to read FLASH, the feedback phenomenon is:
When DATA FLASH is started, the first code EBOOT.nb0 will be stored in the 0X5000 offset address of DATA FLASH. After loading, WINCE will be booted.
But the actual result is:
================================== "RomBOOT "RomBOOT
INFO: Low Level Init: OK StarTIng main... AT45DB321 ...
Load CE-BOOT from Flash to SDRAM Jumping...
===========================================
From the point of view of the phenomenon, DATA FLASH has been found, which means that the SPI line is correct, but why is there a problem with the data read?
The suspected problems are as follows:
First: DATA FLASH SPI itself has hardware problems, there may be interference.
Second: In copying data from DATA FLASH to SDRAM, an error occurs, the data is incorrect, and there is a problem with SDRAM initialization. Third: Because our SPI line is different from the previous version, it is separated by the MAX3002. It is suspected that the MAX3002 itself causes instability of the SPI line.
Fourth: There is a problem with the CPU version. The AT91SAM9263 has been changed from A to B. The SPI has been changed. I know that the AT91SASM9263 B version of the SPI requires two resets to work.
Verification of a suspected problem:
One: SAM BA 2.8 can initialize the SDRAM, and can read and write, indicating that there is no problem in the hardware of the SDRAM itself.
Second: DATA FLASH, SAMBA 2.8 can be read and written without any problems, and the startup code can be executed correctly. Then it should be proved that the SPI part can work, but the problem is that the ROM BOOT of the AT91SAM9263 B version and the ROM BOOT of the AT91SAM9263 A version are different, then it is proved that the initialization part of the SPI part has been corrected. So, find the ERR DATA SHEET of the SPI part of the AT91SAM9263 B version. Looking for a problem. Changed the half-day code, the problem is still the same.
Third: There is really no way. On November 18, 2008, the founder of Baxter was initially identified as a problem with the CPU version. I personally think that my code level is relatively backward, and I requested Leigong to help. The final verification result is as follows:
The data read from DATA FLASH has been problematic after being placed in SDRAM. Our former boss is no problem. Data can be read out from DATA FLASH correctly and then displayed on the serial port. Each time I read 10 bytes from DATA FLASH, I found that the read data is consistent every time, but it is not correct.
There is no way, Leigong has not written code for a long time, but had to make an appointment for the next day, to Bai Te to find their engineer Liu Gong, Liu Gong is my fellow, really enough friends, got in the middle of the night that night, and finally verified, The phenomenon is: the data read from the DATA FLASH offset 0X8000 address is placed in the SDRA M, and a certain location finds the same data. Finally, the result is: It may be that the AT91SAM9263 B version may have problems, but the biggest problem is: After the SDRAM works, it affects the stability of the SPI.
Fourth: It’s too late, everyone went home. (At this time, I found a specific version of the CPU of the A version, saying that they are out of stock now, can be sent the next day), there is really no clue, no The method, quickly set the CPU, AT91SAM9263 A version, just happens, Baxter has no goods, after their boss is set from Hong Kong, we get it, hurry to paste it, this process is only one day, afternoon, 3 pm Just do it well, bring the test software, go to Li Gong (the master of our welding), put all the tools, test, depressed, but still not. God...
Fifth: It seems that the A version is not working. It can only be suspected that there is a problem with the wiring of the board. Because there is no other way to think about it. At this time, I am relaxed because I think the problem has been found. But which line of SPI is disturbed? I am deeply convinced of Baxter Liugong’s words. There is really no way. In the morning, I quickly went to Baxter with the A version of the board and found Liu Gong. (I want to repeat the results of his verification. Liu Gong changed it for a long time and found that it was read from the 0 address of DATA FALSH. Data is put into SDRAM is no problem, I have been suspected of SDARM initialization problems. According to the test results of these days, I found a doubt, I found the A version of the chip, I wrote a small program, read from DATA FLASH It is also incorrect to fetch data into SRAM. Moreover, it is exactly the same as the previous test results. I have always suspected that it has a relationship with the chip. Now, I can completely eliminate the problem of the chip AT91SAM9263.
Sixth: Reading data from DATA FLASH into SRAM is also incorrect (I turned off SDRAM), and I overturned Liu Gong's SDRAM to interfere with SPI DATA FLASH.
Liu Gong found that from the 0 address of DATA FALSH, most of the data is read into SDRAM. This time, all the code is restored. Put the data of DATA FLASH 0 address to 0X23F00000 (LINUX boot program U- BOOT address) -0X8000 position, so that you can ensure that there is a correct U-BOOT program in the position of 0X23F00000. However, when the program is running, it still does not get the correct startup result. It may be that some data is read out and it is still incorrect.
Seventh, there is really no way. We are beginning to suspect that there is a problem with DATA FLASH. I just asked our LISA (LISA is our purchase. I always thought that this DATA FLASH was purchased from Baxter and finally found this. Something was purchased from the market, I was dizzy, but when I asked LISA, I didn't pay attention to it. LISA said that this chip is original), just happened to bring a board of our old version, it will be old. After the version of the board's DATA FLASH is changed, it is completely OK.
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