As 5G millimeter wave is expected to enter commercial use soon, the R & D of key companies in the industry is progressing smoothly, and the specification, design and verification of custom component indicators have been completed. The basic component required to realize the future millimeter wave 5G system is the radio frequency front-end module (FEM). This module includes the final amplifier stage of the transmitter and the front-end amplifier stage in the receiver and the transmit / receive switch (Tx / Rx) to support time division duplex (TDD). FEM must have high linearity in transmit mode and low noise figure in receive mode. The millimeter wave 5G system may require the user terminal to use multiple FEMs to form a phased array architecture or a switched antenna beam architecture. Therefore, FEM must be implemented in an efficient, compact, and low-cost manner, and it is best to simply control and monitor.
This article introduces the design, implementation and verification of the 28GHz 5G communication band (27.5 to 28.35GHz) RF front-end module MMIC (monolithic microwave integrated circuit) that meets all the above requirements. The RF front-end was developed by Plextek RFI, and was implemented using PE-15 4V voltage, 0.15 μm, enhanced GaAs PHEMT process of WINSemiconductors. It uses a compact, low-cost and SMT (surface mount) compatible 5mm x 5mm overmolding compatible QFN package, suitable for high-volume, low-cost manufacturing. It covers 27 to 29GHz, so it supports the full 28GHz 5G band.
1. Design goals
The design of the FEM transmission channel focuses on achieving high efficiency with power back-off to provide linear amplification, which is a requirement of the 5G communication system. The target power added efficiency (PAE) under power back-off is set at 6%, and the third-order intermodulation (IMD3) is lower than -35dBc (power back-off value: about 7dB back from the 1dB compression point). The RF output power corresponding to the 1dB compression point (P1dB) is set at 20dBm. The receiving channel needs to achieve a noise figure (including switching loss) of less than 4dB at a very low current consumption (maximum 15mA, + 4V power supply).
The functional block diagram of the RF front-end MMIC is shown in Figure 1. The transmit signal path extends from the left to the right in the upper half of the figure; the input port is located on the pin labeled "PA_RFin". The input signal is amplified by a three-stage power amplifier (PA) and then connected to the antenna through an RF power detector and a single pole double throw (SPDT) switch. The on-chip directional power detector can monitor the emitted RF output power, and a temperature compensation function is integrated on the chip. The output of the power detector with compensation is determined by the difference between the voltage "Vref" and the voltage "Vdet". The chip integrates a fast switching enable circuit (PA enable circuit in Figure 1) controlled by the (low level active) logic signal "PA_ON". When switching between transmitting and receiving modes, the PA can be quickly powered on and off, so that when the PA is not in use, only 0.1mA of current can be used to maximize the efficiency of the entire system.
Figure 1: Functional block diagram of 28GHz 5G communication RF front-end module chip
The PA will usually work under the condition of a few dB back from the compression point to keep the modulated signal it emits without serious distortion. The design method is to optimize the performance of the power amplifier to work back around 7dB at the P1dB point. In order to achieve a better PAE under this working condition, the PA will be biased in the deep class AB.
2. Design a compromise strategy
The design starts with device-level simulation of candidate cell transistors. This simulation work can obtain key information such as device size, bias point, target impedance, PA series and driver ratio, which lays a solid foundation for the subsequent fine power amplifier design.
An important part of this work is to determine how to maximize the PAE under power back-off. In general, this can be achieved by reducing the static bias current density of the device. However, in this method, the range in which the current density can be adjusted downward is limited by the gain and linearity constraints, because both of them deteriorate as the current density decreases. There is a clear trade-off relationship between PAE and gain under power back-off conditions and linearity.
The main linearity index in the design is that under power back-off conditions, IMD3 must be less than -35dBc. As shown in Figure 2, IMD3 performance is particularly sensitive to fundamental frequency load conditions when the bias current is reduced. Figure 2a shows the load traction simulation results of 8 & TImes; 50μm devices biased to deep AB at 4V, 75mA / mm, and the load corresponding to the PAE optimal point at P1dB is marked. The figure also shows the simulated performance of the IMD3 under the optimal load and power back-off conditions, indicating that there is about 4dB margin from the -35dBc specification. The simulated PAE is about 15% under this power back-off condition, and the efficiency is only included in the effect of the device, excluding any output loss. Figure 2b shows the load and IMD3 corresponding to the optimal point of P1dB power under the same device and bias operating conditions. It is found that under the same relative power back-off situation, the performance of its IMD3 is significantly worse, exceeding the target by more than 5dB, and the PAE is similar to the previous condition at this time, about 15.7%.
Figure 2: The impedance point corresponding to the best PAE under P1dB conditions and the corresponding IMD3 (a) under power back-off conditions; the impedance point corresponding to the best power under P1dB conditions and IMD3 (b) under corresponding power back-off conditions .
Further evaluated the performance of the amplifier under two conditions of P1dB and power back-off at other impedance points on the Smith chart. The load conditions in Figure 2a clearly have the best overall performance and are therefore selected for output stage design. In the end, the 52mA / mm bias current was selected, and the 8x50μm device was selected as the basic unit of the output stage to meet the power specifications. According to the total transmission gain index, it is determined that three-stage amplification is required.
A complete three-stage power amplifier is designed by selecting the optimal transistor size for the driving amplifier stage and the pre-drive amplifier stage in sequence. This also requires careful consideration of design trade-offs because larger transistor sizes can improve overall linearity but lower PAE. When the size and bias of all transistors are determined, the detailed design of the matching and bias circuit can be continued. The layout design needs to be considered from the early stage of the entire design process to avoid introducing excessive parasitic effects and to ensure the realizability of the design. The first and second stages of the power amplifier use a common gate bias lead (added to the pin PA_Vg12), while the third stage sets a separate bias lead (PA_Vg3). In this way, the two voltages can be optimized independently to improve the linearity or PAE of the PA. Drain power supply can similarly apply + 4V voltage to "PA_Vd12" and "PA_Vd3" through two separate pins, although these two pins are connected on the PCB.
The SPDT switch uses a series-parallel structure, and multiple transistors are integrated in the series and parallel branches of the design to improve linearity1. The capacitance when the transistor is off limits the inherent isolation of the device at high frequencies in the off state. The isolation of the switching transistor is only a few dB2 at 28 GHz. Reducing the size of the transistor can improve the inherent isolation, but it will increase the insertion loss in the on-state and reduce its linearity, so it is not a viable option. The method adopted here is to use on-chip inductance compensation to improve off-state isolation. The meticulous design ensures low insertion loss in the on-state to achieve high output power in the transmit channel and low noise figure in the receive channel. The switch is controlled by a bit control voltage "Vctrl1". When this bit is set to 4V, it indicates the transmission mode, and 0V indicates the reception mode. "Single pole double throw control circuit" (SPDT control circuit) can achieve single-bit control, the circuit is essentially a pair of two-wire decoder. The total current consumed by the control circuit and the SPDT itself is only 1mA, provided by the + 4V power applied at "VD_SW".
The input of the receiving channel is located at the "antenna" pin connected to the two-stage LNA input via SPDT. The output of the receive channel is located on the pin labeled "LNA_RFout". Like the PA, the LNA also has a fast switching enabling circuit, so that the LNA consumes only a low current of 0.1mA when not in operation. The key to the design process of a low-noise amplifier is to find a design with low current consumption, good noise figure, and sufficient linearity.
The important first step is to choose the right transistor size. Multiple short interdigitated fingers can be used to reduce the gate resistance of the transistor and improve the noise figure. Both stages of the low-noise amplifier use series inductive feedback to make the impedance required for optimal noise figure closer to the impedance required for conjugate matching and optimal gain.
The first stage of the low-noise amplifier takes the noise figure as the design optimization goal, but it still needs to generate enough gain to fully reduce the influence of the second stage noise figure. The noise figure of the second stage of the low-noise amplifier is not important, so this stage is designed to have a higher gain than the first stage. The designed LNA only needs 10mA DC current of + 4V power supply. The gate bias voltage is applied to the pin "LNA_Vg", and the + 4V drain bias voltage is applied to "LNA_Vd". The "LNA_Vsense" pin provides monitoring of the bias current. The monitored bias current information can be used to control the gate voltage to compensate for changes in environmental conditions such as temperature. Under the correct bias, the voltage of this monitoring pin is 3.9V. The process using enhanced transistors means that only positive supply voltage is required, making MMIC very easy for system integration.
Careful electromagnetic simulation is very important to ensure good RF performance of each module. A gradual addition method is adopted, each time a part of the circuit is added to the EM simulation, while the rest is still simulated using the model in the process design kit (PDK). Since integrated circuits are used in the plastic packaging obtained by the overmolding process, compounds injected above the integrated circuits also need to be considered in electromagnetic simulation.
3. Evaluation and testing
Figure 3 is a photo of the RF front-end chip. The size of the RF front-end MMIC chip is 3.38mm & TImes; 1.99mm. Its pad / pin position is similar to the position shown in the block diagram, and it also integrates multiple ground pads, so that it can be fully on-chip radio frequency test (RFOW). It is designed to use low-cost injection molding 5mm & TImes; 5mmQFN package. And considering the influence of mold plastics, it is necessary to carefully design the RF transition interface from chip to PCB. A customized lead frame is designed to achieve this transition, and the RF ports on the package are designed as a ground-signal-ground (GSG) interface.
Figure 3: The chip photo of the 28GHz 5G communication RF front-end module MMIC
After processing and manufacturing, on-chip RF tests were performed on multiple chips to confirm that the chip reached the design goal of one-time tape-out before packaging. The on-chip RF test results are not given here. All the results given are measured after the chip is fully packaged and mounted on a typical PCB evaluation board.
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