1 Introduction
With the growth of market demand, the integration level and process level of VLSI are continuously improved, and it is possible to complete system-level design on one chip. The inherent parallel processing capability of FPGA makes it able to provide a large number of complex operations required by various digitizations. It is suitable for designing some intelligent controllers that require high processing speed and real-time performance. In recent years, based on the description of VHDL, the design of FPGA-implemented controllers has been relatively active. For example, Torralba et al. Have completed the FPGA implementation of a 4-input, 12-membership, 64-rule fuzzy logic controller [1], Cirstea et al. Based on FPGA design fuzzy controller, successfully used for transmission control [2]. In addition, due to the flexibility and versatility of FPGA design, FPGA-based controllers have high development efficiency, low cost, and short time to market.
Due to the large number of FPGAs used in smart controllers, post-design testing has become a problem that designers must focus on during development. At the same time, a good test method can not only find problems in the design early, but also Improve the reliability of the design. At present, the testing of intelligent controllers based on VHDL generally uses open-loop timing simulation to verify the correctness of its logic design. For some intelligent controllers with input excitation signals that are not fixed or relatively large, open-loop timing simulation is not accurate. The excitation input signal of the analog controller. Therefore, on the basis of open-loop timing simulation, this paper proposes a closed-loop timing simulation test method based on QuartusII, DSP Builder and Modelsim, and makes a more in-depth study on this closed-loop test method with the help of the design of a specific intelligent controller. the study.
2 FPGA design and test platform
The research uses QuartusII4.0, DSP Builder3.0 and Modelsim SE6.0 as FPGA design and test platform.
QuartusII4.0 is Altera's fourth-generation programmable logic device integrated development environment, providing design input, design compilation,
All functions from functional simulation, design processing, timing simulation to device programming. At the same time, it can generate and identify EDIF netlist files, VHDL netlist files and Verilog HDL netlist files, and provides a convenient interface for other EDA tools. Other EDA tools can be automatically run on it, including Synplicity's Synplify / Synplify Pro, Mentor Graphics subsidiary Exemplar Logic's Leonardo Spectrum, and Synopsys' FPGA Compiler II. These comprehensive software can convert VHDL / Verilog design software into a standard netlist file for selected devices with high efficiency. In addition, QuartusII4.0 also integrates a SOPC Builder development tool to support SOPC development [3].
DSP Builder appears in the form of Blockset of Matlab / Simulink, and can be used for graphical design and simulation in Simulink. At the same time, Signal Compiler can convert Matlab / Simulink design files (.mdl) into corresponding VHDL files (.vhd), and TCL script used to control synthesis and compilation [4].
Mentor Graphics' Modelsim is a relatively good simulation tool in the industry. Its simulation function is powerful, supports analog waveform display, and has a friendly graphical interface. It has windows for structure, signal, waveform, process, and data flow.
By comprehensively using the above three platforms, you can plan the design process well, make full use of the advantages of each tool, improve development efficiency, and obtain more reliable test results.
3 VHDL design and test characteristics of intelligent controller
Taking fuzzy self-tuning PID controller as an example, its position control algorithm is:
ui = Kp ei ＋ Ki T∑ei ＋ Kd / T (eiï¼ei-1) ＋ u0 3.1
Among them: Kp = kp + tp & TImes; △ Kp, Ki = ki + TI & TImes; △ Ki, Kd = kd + td & TImes; △ Kd is the real-time parameter of PID controller; △ Kp, △ Ki, △ Kd are the correction values ​​obtained by fuzzy inference. The fuzzy inference process adopts Mamdani direct inference method, and uses the centroid method to obtain the corresponding final accurate value.
The design of fuzzy self-tuning PID controller based on VHDL adopts the top-down design method, and the design and description of each unit module at the RTL level. The structure VHDL is used to connect each unit through the unit map (PORT MAP) to form the entire controller. chip. The core of the controller chip is the control and arithmetic unit, which involves basic data processing, storage and I / O control. The circuit schematic diagram of its top-level module is shown in Figure 1.
Figure 1 Controller schematic diagram of the top module circuit
Among them: control: control module, generate the read and write address of the data in the memory; ram: storage module, store the externally collected data; accum: accumulate module, accumulate 10 times, read the data in the memory; max_min: find Max / Min module , Solve the maximum and minimum value of the collected data; sub: subtraction module, remove Max / Min; average_8: filter module, perform 8 times average filtering on the removed data; compare: compare module, compare with the given value, Generate deviation e; delay: delay module, change rate of deviation ec; fpid: fuzzy self-tuning PID controller module, generate controller output signal.
In this system, A / D adopts AD574A, its conversion speed is maximum 35μs, conversion accuracy is less than or equal to 0.05%. When designing A / D I / O modules with VHDL, the state machine description is used. The state machine is divided into 5 states: STATE0: A / D574 initialization; STATE1: chip select signal generation, start conversion; STATE2: STATUS level monitoring, state switching; STATE3: 8-bit output data is valid; STATE4: by the Lock signal Latch the data.
The test characteristics of the intelligent controller based on the description of VHDL language are: the controller module can be used as an independent module to test the correctness of its logic function through the open-loop timing test benchmark. However, for the control system, we are more concerned about the time response process of the system output under the action of the typical input signal, including dynamic process and steady state process, so it is particularly necessary to use closed-loop timing test.
4 FPGA-based intelligent controller open-loop timing test
The open-loop timing test mechanism of the FPGA-based intelligent controller is to verify whether the controller design meets the design requirements by connecting the excitation entity and the module under test and comparing the output response value of the module under test with the expected value. The designer can use Quartus II software The waveform editor generates a vector waveform file (.vwf) as a simulator excitation, or a text-based vector file (.vec) can be used as the simulator excitation. Among them, VWF uses a graphical waveform to describe the input vector and output of the simulation, while VEC uses a special format file to add excitation to the input signal and vector in the module [5], which is currently in the design. The most commonly used test method. The open loop timing simulation test of fuzzy self-tuning PID controller is shown in Figure 2.
Figure 2 Controller open-loop timing simulation diagram
Figure 2 shows the simulation results of the closed-loop output timing of the fuzzy self-tuning PID controller based on Altera's FPGA device EP20K200EQC240-1.
Among them: clk: system clock; clkc: controller sampling clock; reset: system reset signal; e: deviation; ec: deviation rate of change; u: controller output.
Timing simulation result parameters: Total logic elements: 1092 / 8,320 (25%); Total memory bits: 4096 / 106,496 (3%); Clk setup: 38.86 MHz; Clkc setup: 221.39 MHz; Tsu: 8.864 ns; Tco: 7.809 ns .
The excitation signal deviation e and deviation change rate ec of the controller in Figure 2 are manually edited by the waveform editor, and the input is relatively cumbersome. Their values ​​are obtained by means of MATLAB simulation curves, so they cannot fully simulate the real-time of the intelligent controller. Excitation signal. In order to better simulate the input behavior of the controller and make the test results more reliable, based on the above test, this paper proposes a new closed-loop timing test method for intelligent controllers based on FPGA design tools QuartusII, DSP Builder, and Modelsim.
5 FPGA-based intelligent controller closed-loop timing test
In the design of automatic control systems, the design and test of the controller usually use a closed-loop control system, and determine whether the performance of the controller meets the design requirements by observing the output of the object. Altera's digital signal processing tool DSP Builder, combined with MathWorks' Matlab and Simulink, provides a new test method for the design made in Quartus II. The test process used in this study is as follows: First, use DSP Builder to build the test module in Simulink of Matlab. After running without errors, use Signal Compiler to convert the (.mdl) file into a TCL script file and VHDL file that Modelsim can recognize, followed by , Set the generated VHDL file and TCL script, and finally, run the test file in Modelsim to view the test results. The block diagram of the fuzzy self-tuning PID controller under DSP Builder is shown in Figure 3. The fpid module in the figure is a user-defined module, which is imported through the SubSystemBuilder module of DSP Builder. Using this module, the input and output pin signals of the VHDL design file in QuartusII can be easily introduced into the Simulink system.
Figure 3 DSP Builder module test chart of fuzzy self-tuning PID controller
Run Signal Compiler to generate the TCL script file used in Modelsim, because the user-defined modules added in Simulink appear in the form of black boxes, therefore, the fuzzy self-tuning PID controllers should be Add the module file to the TCL script file. For example, to add the submodule file pid.vhd to the TCL script file, use vcom -93 -explicit -work work "$ workdir / pid.vhd".
Pay attention to the following two points when using DSP Builder:
(1) If the PLL module from the Rate Change library is not used, in the process of Simulink design conversion into a hardware system, DSP Builder will use synchronous design rules, that is, all DSP Builder timing modules in the design system (such as The Delay1 module in Figure 3) works synchronously with the rising edge of a single clock, and this clock frequency is the sampling frequency of the entire system. For these modules, the clock pins will not be directly displayed on the Simulink design drawing, but when using Signal Compiler to convert the design into a VHDL file, the system will automatically connect the clock pins of the timing module together with the The single clocks of the system are connected.
(2) When adding a customized VHDL design entity to the DSP Builder design system, even if the synchronous reset and clock signals have been used in the original design, the synchronous clear and clock input signals must be defined in the entity. Moreover, these two input signals must be connected to the global clock pin and global synchronization clear pin of the target device. If the entity does not need a clock or global synchronization clear pin, these input signals should also be defined, just do not connect.
Taking the controlled object G (s) = 4.71 × e-0.15s / (0.4s + 1) (1.2s + 1) as an example, considering the influence of A / D and D / A, a zero-order retainer (1 ï¼E-TS) / S, the output curve of the closed-loop control system in Modelsim is shown in Figure 4. The given value of the system is 127 (relative gain is 0.992), and the output value rises from 0 to the peak value 148 (relative gain is 1.156) Afterwards, it quickly fell back and finally stabilized at 127. The test results were basically the same as the simulation results of MATLAB.
Figure 4 System closed-loop output curve
6 Conclusion
(1) Building an intelligent controller based on FPGA has the advantages of flexible design, online adjustment, high reliability, and short development cycle. Especially suitable for small and medium-sized systems.
(2) Use QuartusII to design the VHDL of the intelligent controller, and use DSP Builder and Modelsim to perform closed-loop test on the design made in QuartusII, which solves the problem of the input source of the test sample and the input sample extraction of the controller, which can effectively simulate the control The input behavior of the device improves the flexibility of design and testing. At the same time, the test results are reliable and more convincing.
(3) Use DSP Builder and Modelsim to get rid of our previous testing habits. The excitation input signal of the controller can easily call Simulink's modules. The objects can also be flexibly changed according to the need, no need to write in VHDL language, and Modelsim supports The analog waveform display of the signal allows us to see the most intuitive graph.
(4) Testing plays a decisive role in system design. It runs through the entire design. It uses closed-loop timing test methods, combined with DSP Builder and Modelsim to complete the tests of intelligent controllers in various stages. It is a good test method after experimental verification. It is suitable for designs such as controllers that require closed-loop inspection of their control quality.
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