FPGA (Field-Programmable Gate Array), which is a field-programmable gate array, is a product further developed on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application specific integrated circuits (ASIC), which not only solves the shortcomings of the custom circuit, but also overcomes the shortcomings of the limited number of original programmable device gates.
This article is mainly about the design of FPGA-based UART modules, together with detailed information.
In computer data communication, peripherals generally cannot be directly connected to a computer, and the information exchange between them mainly has the following problems:
(1) The speed does not match. The working speed of peripherals is different from the working speed of computers, and the working speed between peripherals is also quite different.
(2) The data format does not match. Different peripherals may have different data formats when storing and processing information. For example, the most basic data formats can be divided into parallel data and serial data.
(3) The information types do not match. Different peripherals may use different types of models, some are analog signals, some are digital signals, so the processing is different.
In order to solve the problem of information exchange between peripherals and computers, it is necessary to design an intermediate part of information exchange - interface. The UART controller is the most commonly used interface.
The Universal Asynchronous Receiver-Transmitter (UART) is a communication between the auxiliary computer and the serial device. As an important part of the RS 232 communication interface, most of the processors currently integrate the UART.
First, the UART data format
The data transmission format of the UART is shown in Figure 1.
Since the digital image sub-pixel is represented by an 8-bit binary in the computer, the valid data bit transmitted by the UART is 8 bits. The transmission line is high when idle, so the start bit of the active data stream is set to zero. The 8-bit valid data bit is then transmitted, starting with the lowest bit.
The parity bit can be set to odd parity, even parity or no parity. Since the transmission rate used by this system is not high, in order to speed up the development process and reduce the circuit area, the parity module is not designed, and the data stream is not set. Parity bit. The last stop bit is high.
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