Hello, everyone, it's time to study everyday. Since its introduction in 1985, FPGAs, such as programmable logic devices, have gained a place in communications, medical, industrial control, and security by virtue of their advantages in performance, time-to-market, cost, stability, and long-term maintenance. Especially in the past two years, with the prosperity of cloud computing, high-performance computing and artificial intelligence, FPGAs with inherent advantages have received unprecedented attention. In recent years, as the country began to vigorously develop the industry, the domestic integrated circuit industry has been getting better and better, and as the user's requirements for performance have become higher and higher, the FPGA is programmable, high speed, low power consumption, and low The superior features of secondary development costs have led to the development of the FPGA industry, and many students have started to learn FPGAs.
First of all, first look at FPGA, FPGA: Field-Programmable Gate Array, Chinese name: Field Programmable Gate Array. The FPGA consists of six parts: Programmable Input/Output Units, Elementary Programmable Logic Units, Embedded Block RAMs, Rich Cabling Resources, Embedded Embeddable Functional Units, and Built-in Dedicated Hard Cores. Intel Chief Executive Officer Korczyn once described: "You can think of an FPGA as a bunch of gates that can be programmed at any time. FPGAs can be used as accelerators in multiple areas, such as performing face searches while encrypting, and in microseconds. Reprogramming. Its cost is much lower than large-scale single custom parts, and has higher flexibility."
The FPGA is a programmable device. Compared with the traditional logic circuits and gate arrays (such as PAL, GAL, and CPLD devices), the FPGA has a different structure. The FPGA uses a small lookup table (16×1 RAM) to implement the combinational logic. Each lookup table is connected. To the input of a D flip-flop, the flip-flop drives other logic circuits or drives the I/O, thereby constituting a basic logic unit module that can realize both combinational logic functions and sequential logic functions. These modules use metal links. Lines are connected to each other or to I/O modules. FPGA logic is implemented by loading programming data into internal static memory cells. Values ​​stored in memory cells determine the logic functions of logic cells and the connection between modules or modules and I/O, and ultimately determine the FPGA can realize the function, FPGA allows infinite programming.
The following figure shows the structure of a four-input lookup table.
The following figure shows the FPGA architecture (example Intel AlteraCyclone II EP2C20)
The introduction of FPGA concepts and structures, etc. is here. If you want to know more about them, you can read the data yourself. Next, let's talk about what knowledge or small details you need to pay attention to when learning a beginner FPGA. Hopefully, it will help everyone learn.
************************************************** ************************************************** ***********************
***Different types of hardware and software***
************************************************** ************************************************** ***********************
*** Universal Application Software***
a. Software assembly language (Assembly Language) is a machine-oriented programming language.
b. The main concern is logic and abstraction. The complexity is controlled after the amount of code is large. There are many hardware resources, and the hardware performance varies greatly. There is no need to design for specific resources.
c. There are more logical layers, and the loss of performance from abstraction is acceptable. Even today, many mainstream languages ​​are built on virtual machines and interpreters.
d. Non-real time.
e. Do not need to understand the underlying hardware principles.
************************************************** ************************************************** ***********************
*** Embedded Software (Hardware Programming)***
a. The timing is controllable. Most scenarios require real-time because of the hardware timing. Non-preemptive task scheduling and interrupt queues introduce timing offsets.
b. Controllable resource costs. Most embedded hardware environments have limited RAM and Flash resources.
c. Designed for a specific hardware environment.
d. All code abstraction and optimization must be zero loss or controllable loss (see rust language). It is typical that GC introduces severe timing and resources that are not controllable, so system languages ​​are rarely used.
************************************************** ************************************************** ***********************
***Digital logic circuit design (hardware descriptive language)***
a. Digital circuit design is not programming. It is the design of the first circuit, and then describe the language.
b. The timing requirements are more stringent and the setup and hold times need to be considered, along with the consequent meta-stable state.
c. Coding style will obviously affect the circuit performance. The logic is the same, but the location of the DFF is not the same, it may cause the timing is not satisfied.
d. Parallelization. The execution order is no longer the sequential execution of the CPU, but multiple parallel pipelines. For example, Fast Fourier FFT. For example, the CAM of the router completes the entire table look-up table in a single action.
************************************************** ************************************************** ***********************
1. VHDL and verilog HDL used in FPGA learning is not a programming language but a comprehensive hardware description language. We must understand what kind of circuit we want to design when we describe it.
2. Verilog HDL language is used for development in modern society. Verilog HDL supports two processes: initial and always. The former can only be used in TB (TestBench), and the latter is synthesizable.
3. Both blocking and non-blocking fingers are relative to the process itself. In simple terms, blocking is used to describe combinatorial logic circuits rather than blocking them for sequential logic circuits.
4. Use the circuit type of the process module:
Combined Circuits - Sensitive to all inputs used in combinatorial logic Example:
Always@(a or b or c)
Sequential circuit - only sensitive to clock and control signals Example:
Always @(posedge clk or negedge rst_n)
Always can describe combinatorial logic as well as sequential logic.
5. You can use the case statement to complete the function of the multiplexer, but the list must be considered fully, otherwise it will produce Latch.
There are two types of subroutines in verilog:
Functions and Tasks Function ----- Returns a value based on input ----- Produces combinatorial logic ----- Used in expressions: assign mult_out=mult(ina,inb);
-----Functions are combinatorial logic and cannot contain any delay, event, or timing control declarations. At least one input variable always returns a variable ----- functions can be called but tasks cannot be called.
Task ----- can be a combination or register ----- call the task in the form of a statement: stm_out (nxt, first, sel, filter);
-----Similar to tasks in other programming languages ​​- Different tasks do not need to pass parameters, and functions pass parameters
----- You can call tasks and functions.
----- Can contain any delay, event, or timing control statement
----- Return zero or more values
The synthesizable verilog syntax subset refers to the syntax that can be implemented in hardware. Strive to implement the most complex hardware circuit in the simplest language.
7. The hardware has corresponding input and output interfaces, either input or output, or input and output.
8. The reg type refers to a register data (register type) in the sequential logic, and wire is a connection (line type) in the combinational logic.
9. define defines a parameter that is effectively used throughout the project. A parameter defined by parameter is used only in the current file.
10. Various logical operators, shift operators, and arithmetic operators are mostly synthesizable.
11. assign is generally only for combinatorial logic, while the always statement can be used for combinational logic and can be used for sequential logic, always sensitive table, if it is level, it is combinational logic, if it is along the signal posedge or negedge It is sequential logic.
12. The begin----end is similar to {} in the C language.
13. for statement ----- loop Because the integrated result may be a waste of resources, it is generally used less, but in some specific designs can have a multiplier effect.
14. Total logic element Total consumed logical unit.
15. Behavioral simulation can be understood as functional simulation (pre-simulation); post-placement simulation can be understood as timing simulation (post-simulation).
16. The clock and reset signals are necessary in the timing logic.
17. A problem with wire assignments is as follows:
Wire[2:0] key_an=key_rst_r&(~key_rst)
It is equivalent to the following assignment statement wire[2:0] key_an;
Assign key_an=key_rst_r&(~key_rst);
Its effect is the same.
This method is: Pulse edge detection method.
18. In practice, in addition to the use of for loop statements when describing the simulation test stimulus (Testbench), the for loop is rarely used in RTL level coding because the for loop is expanded by the synthesizer to execute statements for all variables. Each variable occupies register resources independently, and cannot effectively reuse hardware logic resources, causing huge waste. Generally used case statements instead.
19. The general FPGA trigger resources are rich, and CPLD combination logic resources are more abundant.
20. Two languages ​​used by FPGAs: VHDL and verilog HDL.
VHDL was invented by the U.S. Department of Defense and used for large-scale projects (more than one million gates) completed by a large number of designers. The grammar/structure is more rigorous because the style of the modules written is clear.
Verilog HDL has more third-party support tools, and its syntax is simpler than VHDL. It is easier to learn, simulation tools are easier to use, and the test stimulus module is easy to write.
21. The essence of timing design: The difficulty of circuit design lies in the timing design. The essence is to meet the requirements of a trigger setup/hold time.
(Remarks: Settling time: the minimum time the data input must remain unchanged before the rising edge of the clock; the hold time: After the trigger arrives at the rising edge of the clock, the trigger will come before the rising edge of the clock. The data input must remain unchanged for the minimum time.)
22. Why do triggers meet setup and hold times?
Since the formation of the internal data of the flip-flop requires a certain amount of time, if the setup and hold times are not met, the flip-flop will enter a meta-stable state. After entering the meta-stable state, the output of the flip-flop will be unstable and change between 0 and 1. At this time, it takes a recovery time before the output can be stabilized, but the stabilized value is not necessarily your input value. This is why two-stage triggers are used to synchronize asynchronous input signals. Doing so can prevent the metastable generated by the flip-flop of this stage from propagating into the following logic due to the asynchronous input signal may not satisfy the setup and hold time for the current stage clock, resulting in the propagation of the metastable state.
23. What is the difference between latch and flip-flop?
Level-sensitive memory devices are called latches. Can be divided into high-level latches and low-level latches for signal synchronization between different clocks.
A bistable memory element constructed with cross-coupled gates is called a flip-flop. Divided into rising edge trigger and falling edge trigger. Think of two different level-sensitive latches in series. The previous latch determines the settling time of the flip-flop, and the latter latch determines the hold time.
24. and so on.
Finally, let's briefly talk about the scope of application of FPGA. FPAG has become more and more widely used, aerospace, automotive driving, medical, broadcast, measurement and testing, consumer electronics, industrial control, computer equipment, weapons and equipment. From the perspective of application scenarios, we can see that as Google’s Alpha Dog defeated the human Go Championship, deep learning has already gone down from the altar, and more and more people are beginning to realize that deep learning may change the future of life. It becomes the direction of future science and technology development; FPGA design tools make it more compatible with the upper-level software that is often used in deep learning. FPGA is a big technology that helps deep learning. Unlike the CPU, FPGAs and GPUs have a large number of computing units, so their computing power is very strong. When performing neural network operations, both are much faster than the CPU. However, the GPU is fixed because of the native support of the fixed hardware, and the FPGA is programmable.
With the country's overall strength becoming more and more powerful, the national economy is getting better and better. FPGAs have gradually extended from the previously widely used military industry to the civil industry and will become more and more extensive.
We will talk about the little knowledge of FPGA learning here. If you still want to know more about it, you can discuss it with the landlord and welcome you to leave a message.
Come on, everyone! Study hard and improve every day.
First of all, first look at FPGA, FPGA: Field-Programmable Gate Array, Chinese name: Field Programmable Gate Array. The FPGA consists of six parts: Programmable Input/Output Units, Elementary Programmable Logic Units, Embedded Block RAMs, Rich Cabling Resources, Embedded Embeddable Functional Units, and Built-in Dedicated Hard Cores. Intel Chief Executive Officer Korczyn once described: "You can think of an FPGA as a bunch of gates that can be programmed at any time. FPGAs can be used as accelerators in multiple areas, such as performing face searches while encrypting, and in microseconds. Reprogramming. Its cost is much lower than large-scale single custom parts, and has higher flexibility."
The FPGA is a programmable device. Compared with the traditional logic circuits and gate arrays (such as PAL, GAL, and CPLD devices), the FPGA has a different structure. The FPGA uses a small lookup table (16×1 RAM) to implement the combinational logic. Each lookup table is connected. To the input of a D flip-flop, the flip-flop drives other logic circuits or drives the I/O, thereby constituting a basic logic unit module that can realize both combinational logic functions and sequential logic functions. These modules use metal links. Lines are connected to each other or to I/O modules. FPGA logic is implemented by loading programming data into internal static memory cells. Values ​​stored in memory cells determine the logic functions of logic cells and the connection between modules or modules and I/O, and ultimately determine the FPGA can realize the function, FPGA allows infinite programming.
The following figure shows the structure of a four-input lookup table.
The following figure shows the FPGA architecture (example Intel AlteraCyclone II EP2C20) 
The following figure shows the structure of the FPGA
The introduction of FPGA concepts and structures, etc. is here. If you want to know more about them, you can read the data yourself. Next, let's talk about what knowledge or small details you need to pay attention to when learning a beginner FPGA. Hopefully, it will help everyone learn.
************************************************** ************************************************** ***********************
***Different types of hardware and software***
************************************************** ************************************************** ***********************
*** Universal Application Software***
a. Software assembly language (Assembly Language) is a machine-oriented programming language.
b. The main concern is logic and abstraction. The complexity is controlled after the amount of code is large. There are many hardware resources, and the hardware performance varies greatly. There is no need to design for specific resources.
c. There are more logical layers, and the loss of performance from abstraction is acceptable. Even today, many mainstream languages ​​are built on virtual machines and interpreters.
d. Non-real time.
e. Do not need to understand the underlying hardware principles.
************************************************** ************************************************** ***********************
*** Embedded Software (Hardware Programming)***
a. The timing is controllable. Most scenarios require real-time because of the hardware timing. Non-preemptive task scheduling and interrupt queues introduce timing offsets.
b. Controllable resource costs. Most embedded hardware environments have limited RAM and Flash resources.
c. Designed for a specific hardware environment.
d. All code abstraction and optimization must be zero loss or controllable loss (see rust language). It is typical that GC introduces severe timing and resources that are not controllable, so system languages ​​are rarely used.
************************************************** ************************************************** ***********************
***Digital logic circuit design (hardware descriptive language)***
a. Digital circuit design is not programming. It is the design of the first circuit, and then describe the language.
b. The timing requirements are more stringent and the setup and hold times need to be considered, along with the consequent meta-stable state.
c. Coding style will obviously affect the circuit performance. The logic is the same, but the location of the DFF is not the same, it may cause the timing is not satisfied.
d. Parallelization. The execution order is no longer the sequential execution of the CPU, but multiple parallel pipelines. For example, Fast Fourier FFT. For example, the CAM of the router completes the entire table look-up table in a single action.
************************************************** ************************************************** ***********************
1. VHDL and verilog HDL used in FPGA learning is not a programming language but a comprehensive hardware description language. We must understand what kind of circuit we want to design when we describe it.
2. Verilog HDL language is used for development in modern society. Verilog HDL supports two processes: initial and always. The former can only be used in TB (TestBench), and the latter is synthesizable.
3. Both blocking and non-blocking fingers are relative to the process itself. In simple terms, blocking is used to describe combinatorial logic circuits rather than blocking them for sequential logic circuits.
4. Use the circuit type of the process module:
Combined Circuits - Sensitive to all inputs used in combinatorial logic Example:
Always@(a or b or c)
Sequential circuit - only sensitive to clock and control signals Example:
Always @(posedge clk or negedge rst_n)
Always can describe combinatorial logic as well as sequential logic.
5. You can use the case statement to complete the function of the multiplexer, but the list must be considered fully, otherwise it will produce Latch.
There are two types of subroutines in verilog:
Functions and Tasks Function ----- Returns a value based on input ----- Produces combinatorial logic ----- Used in expressions: assign mult_out=mult(ina,inb);
-----Functions are combinatorial logic and cannot contain any delay, event, or timing control declarations. At least one input variable always returns a variable ----- functions can be called but tasks cannot be called.
Task ----- can be a combination or register ----- call the task in the form of a statement: stm_out (nxt, first, sel, filter);
-----Similar to tasks in other programming languages ​​- Different tasks do not need to pass parameters, and functions pass parameters
----- You can call tasks and functions.
----- Can contain any delay, event, or timing control statement
----- Return zero or more values
The synthesizable verilog syntax subset refers to the syntax that can be implemented in hardware. Strive to implement the most complex hardware circuit in the simplest language.
7. The hardware has corresponding input and output interfaces, either input or output, or input and output.
8. The reg type refers to a register data (register type) in the sequential logic, and wire is a connection (line type) in the combinational logic.
9. define defines a parameter that is effectively used throughout the project. A parameter defined by parameter is used only in the current file.
10. Various logical operators, shift operators, and arithmetic operators are mostly synthesizable.
11. assign is generally only for combinatorial logic, while the always statement can be used for combinational logic and can be used for sequential logic, always sensitive table, if it is level, it is combinational logic, if it is along the signal posedge or negedge It is sequential logic.
12. The begin----end is similar to {} in the C language.
13. for statement ----- loop Because the integrated result may be a waste of resources, it is generally used less, but in some specific designs can have a multiplier effect.
14. Total logic element Total consumed logical unit.
15. Behavioral simulation can be understood as functional simulation (pre-simulation); post-placement simulation can be understood as timing simulation (post-simulation).
16. The clock and reset signals are necessary in the timing logic.
17. A problem with wire assignments is as follows:
Wire[2:0] key_an=key_rst_r&(~key_rst)
It is equivalent to the following assignment statement wire[2:0] key_an;
Assign key_an=key_rst_r&(~key_rst);
Its effect is the same.
This method is: Pulse edge detection method.
18. In practice, in addition to the use of for loop statements when describing the simulation test stimulus (Testbench), the for loop is rarely used in RTL level coding because the for loop is expanded by the synthesizer to execute statements for all variables. Each variable occupies register resources independently, and cannot effectively reuse hardware logic resources, causing huge waste. Generally used case statements instead.
19. The general FPGA trigger resources are rich, and CPLD combination logic resources are more abundant.
20. Two languages ​​used by FPGAs: VHDL and verilog HDL.
VHDL was invented by the U.S. Department of Defense and used for large-scale projects (more than one million gates) completed by a large number of designers. The grammar/structure is more rigorous because the style of the modules written is clear.
Verilog HDL has more third-party support tools, and its syntax is simpler than VHDL. It is easier to learn, simulation tools are easier to use, and the test stimulus module is easy to write.
21. The essence of timing design: The difficulty of circuit design lies in the timing design. The essence is to meet the requirements of a trigger setup/hold time.
(Remarks: Settling time: the minimum time the data input must remain unchanged before the rising edge of the clock; the hold time: After the trigger arrives at the rising edge of the clock, the trigger will come before the rising edge of the clock. The data input must remain unchanged for the minimum time.)
22. Why do triggers meet setup and hold times?
Since the formation of the internal data of the flip-flop requires a certain amount of time, if the setup and hold times are not met, the flip-flop will enter a meta-stable state. After entering the meta-stable state, the output of the flip-flop will be unstable and change between 0 and 1. At this time, it takes a recovery time before the output can be stabilized, but the stabilized value is not necessarily your input value. This is why two-stage triggers are used to synchronize asynchronous input signals. Doing so can prevent the metastable generated by the flip-flop of this stage from propagating into the following logic due to the asynchronous input signal may not satisfy the setup and hold time for the current stage clock, resulting in the propagation of the metastable state.
23. What is the difference between latch and flip-flop?
Level-sensitive memory devices are called latches. Can be divided into high-level latches and low-level latches for signal synchronization between different clocks.
A bistable memory element constructed with cross-coupled gates is called a flip-flop. Divided into rising edge trigger and falling edge trigger. Think of two different level-sensitive latches in series. The previous latch determines the settling time of the flip-flop, and the latter latch determines the hold time.
24. and so on.
Finally, let's briefly talk about the scope of application of FPGA. FPAG has become more and more widely used, aerospace, automotive driving, medical, broadcast, measurement and testing, consumer electronics, industrial control, computer equipment, weapons and equipment. From the perspective of application scenarios, we can see that as Google’s Alpha Dog defeated the human Go Championship, deep learning has already gone down from the altar, and more and more people are beginning to realize that deep learning may change the future of life. It becomes the direction of future science and technology development; FPGA design tools make it more compatible with the upper-level software that is often used in deep learning. FPGA is a big technology that helps deep learning. Unlike the CPU, FPGAs and GPUs have a large number of computing units, so their computing power is very strong. When performing neural network operations, both are much faster than the CPU. However, the GPU is fixed because of the native support of the fixed hardware, and the FPGA is programmable.
With the country's overall strength becoming more and more powerful, the national economy is getting better and better. FPGAs have gradually extended from the previously widely used military industry to the civil industry and will become more and more extensive.
We will talk about the little knowledge of FPGA learning here. If you still want to know more about it, you can discuss it with the landlord and welcome you to leave a message.
Come on, everyone! Study hard and improve every day.
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