These chip package types are basically all

1, BGA (ball grid array)

One of the spherical contact display, surface mount packages. A spherical bump is formed on the back surface of the printed substrate in place of the lead, and the LSI chip is mounted on the front surface of the printed substrate, and then sealed by a molding resin or a potting method. Also known as a bump display carrier (PAC). The pin can exceed 200 and is a package for multi-pin LSI.

The package body can also be made smaller than the QFP (four-sided pin flat package). For example, a 360-pin BGA with a 1.5mm center-to-center distance is only 31mm square; a 304-pin QFP with a 0.5mm center-to-center distance is 40mm square. And BGA doesn't have to worry about pin deformation like QFP. The package was developed by Motorola Inc. of the United States and was first adopted in devices such as cellular phones, and is likely to become popular in personal computers in the United States in the future .

Initially, the BGA has a pin (bump) center-to-center distance of 1.5mm and a pin count of 225. There are also some LSI manufacturers that are developing 500-pin BGAs. The problem with BGA is the visual inspection after reflow soldering. It is not clear whether an effective visual inspection method is available. Some believe that because the center distance of the weld is large, the connection can be regarded as stable and can only be handled by functional inspection. The Motorola Company of the United States refers to the package sealed with molded resin as OMPAC, and the package sealed by the potting method is called GPAC (see OMPAC and GPAC).

2, BQFP (quad flat package with bumper)

Quad flat-lead package with pad. One of the QFP packages has protrusions (cushions) at the four corners of the package body to prevent bending deformation of the pins during shipping. US semiconductor manufacturers use this package primarily in circuits such as microprocessors and ASICs. The center of the pin is 0.635mm and the number of pins is from 84 to 196 (see QFP).

3. Butt joint pin grid array

Another name for surface mount PGA (see surface mount PGA).

4, C-(ceramic)

Indicates the mark of the ceramic package. For example, CDIP stands for ceramic DIP. It is a mark that is often used in practice.

5, Cerdip

Glass-sealed ceramic dual in-line package for circuits such as ECL RAM, DSP (Digital Signal Processor). Cerdip with glass window is used for UV-erasing EPROM and internal microcomputer circuit with EPROM. The center of the pin is 2.54mm and the number of pins is from 8 to 42. In Japan, this package is indicated as DIP-G (G is the meaning of a glass seal).

6, Cerquad

One of the surface mount packages, the bottom sealed ceramic QFP, is used to package logic LSI circuits such as DSP. Cerquad with a window is used to encapsulate the EPROM circuit. The heat dissipation is better than that of the plastic QFP, and the power of 1.5 to 2 W can be tolerated under natural air cooling conditions. However, the packaging cost is 3 to 5 times higher than that of plastic QFP. The center distance of the pins is 1.27mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm and other specifications. The number of pins is from 32 to 368.

7, CLCC (ceramic leaded chip carrier)

A ceramic chip carrier with a lead, one of the surface mount packages, with leads drawn from the four sides of the package in a T-shape. A window-mounted package for UV-erasing EPROMs and microcomputer circuits with EPROMs. This package is also known as QFJ, QFJ-G (see QFJ).

8, COB (chip on board)

The chip-on-board package is one of the bare chip mounting technologies. The semiconductor chip is placed on the printed circuit board. The electrical connection between the chip and the substrate is realized by the wire stitching method. The electrical connection between the chip and the substrate is realized by the wire stitching method. Resin coverage to ensure reliability. Although COB is the simplest bare chip placement technology, its packaging density is far less than TAB and rewind soldering technology.

9, DFP (dual flat package)

Double-sided pin flat package. It is another name for SOP (see SOP). I used to have this method before, but now I have basically not used it.

10, DIC (dual in-line ceramic package)

Another name for ceramic DIP (including glass seal) (see DIP).

11, DIL (dual in-line)

Another name for DIP (see DIP). European semiconductor manufacturers use this name more.

12, DIP (dual in-line package)

Dual in-line package. One of the plug-in packages, the leads are led out from both sides of the package, and the package materials are plastic and ceramic. DIP is the most popular plug-in package, and its application range includes standard logic IC, memory LSI, and microcomputer circuit.

The pin center is 2.54mm apart and the number of pins is from 6 to 64. The package width is typically 15.2mm. Some packages with widths of 7.52mm and 10.16mm are called skinny DIP and slim DIP (narrow body DIP). However, in most cases, there is no distinction. They are simply referred to as DIP. In addition, ceramic DIP sealed with low melting glass is also known as cerdip (see cerdip).

13, DSO (dual small out-lint)

Double-sided pin small outline package. Another name for SOP (see SOP). Some semiconductor manufacturers use this name.

14, DICP (dual tape carrier package)

Double-sided pin-loaded package. One of TCP (loaded package). The leads are fabricated on the insulating tape and pulled out from both sides of the package. Due to the TAB (Automatic On-Load Soldering) technology, the package is very thin. It is commonly used in liquid crystal display driver LSIs, but most of them are fixed products. In addition, a 0.5mm thick memory LSI booklet package is in the development stage. In Japan, DICP is named DTP according to the EIAJ (Japan Electromechanical Industry) standard.

15, DIP (dual tape carrier package)

Ibid. The name of DTCP is standard by the Japan Electromechanical Industry Association (see DTCP).

16, FP (flat package)

Flat package. One of the surface mount packages. Another name for QFP or SOP (see QFP and SOP). Some semiconductor manufacturers use this name.

17, flip-chip

Reverse soldering chips. One of the bare chip packaging technologies is to form metal bumps in the electrode regions of the LSI chip, and then bond the metal bumps to the electrode regions on the printed substrate. The footprint of the package is essentially the same as the chip size. It is the smallest and thinnest of all packaging technologies. However, if the thermal expansion coefficient of the substrate is different from that of the LSI chip, a reaction occurs at the joint, thereby affecting the reliability of the connection. Therefore, it is necessary to reinforce the LSI chip with a resin and use a substrate material having substantially the same thermal expansion coefficient.

18, FQFP (fine pitch quad flat package)

The small pin center is from the QFP. Usually refers to a QFP with a pin pitch less than 0.65mm (see QFP). Some conductor manufacturers use this name.

19. CPAC (globe top pad array carrier)

Another name for BGA in the US Motorola company (see BGA).

20, CQFP (quad fiat package with guard ring)

Quad flat-lead package with guard ring. One of the plastic QFPs, the pins are masked with a resin protection ring to prevent bending deformation. Before assembling the LSI on the printed circuit board, the pin is cut from the guard ring and made into a seagull wing shape (L shape). This package has been mass produced in Motorola, USA. The center of the pin is 0.5mm, and the number of pins is up to 208.

21, H-(with heat sink)

Indicates a mark with a heat sink. For example, HSOP stands for SOP with a heat sink.

22, pin grid array (surface mount type)

Surface mount PGA. Usually the PGA is a cartridge type package with a lead length of approximately 3.4 mm. The surface mount PGA has a display-like pin on the underside of the package, ranging in length from 1.5mm to 2.0mm. The mounting method is a method of bump welding with a printed substrate, and is therefore also referred to as a bump-welded PGA.

Because the pin center distance is only 1.27mm, which is less than half of the plug-in type PGA, the package body can be made not very large, and the pin count is more than the plug-in type (250~528), which is a package for large-scale logic LSI. . The packaged substrate has a multilayer ceramic substrate and a glass epoxy printing base. Packaging with a multilayer ceramic substrate has been put to practical use.

23. JLCC (J-leaded chip carrier)

J-shaped pin chip carrier. Refers to the window CLCC and the ceramic QFJ with window (see CLCC and QFJ). The name adopted by some semiconductor manufacturers.

24, LCC (Leadless chip carrier)

Leadless chip carrier. Refers to the surface mount package with no electrodes on the four sides of the ceramic substrate. It is a package for high speed and high frequency ICs, also known as ceramic QFN or QFN-C (see QFN).

25, LGA (land grid array)

Contact display package. That is, a package having an array state electrode contact is fabricated on the bottom surface. Plug in the socket when assembling. A practical ceramic LG with 227 contacts (1.27mm center distance) and 447 contacts (2.54mm center distance) is now available for high speed logic LSI circuits.

Compared to QFP, LGA can accommodate more I/O pins in a smaller package. In addition, since the impedance of the lead is small, it is suitable for high-speed LSI. However, due to the complexity of the socket production and the high cost, it is basically not used very much now. It is expected that its demand will increase in the future.

26, LOC (lead on chip)

On-chip lead package. One of the LSI package technologies, the front end of the lead frame is a structure above the chip, and a bump is formed near the center of the chip, and is electrically connected by wire bonding. The chip accommodated in the same size package has a width of about 1 mm compared to the structure in which the lead frame is originally disposed near the side of the chip.

27. LQFP (low profile quad flat package)

Thin QFP. Refers to the QFP with a package body thickness of 1.4mm, which is the name used by the Japan Electromechanical Industry Association according to the new QFP form factor.

28, L-QUAD

One of the ceramic QFPs. The package substrate is made of aluminum nitride, and the base thermal conductivity is 7 to 8 times higher than that of alumina, and has good heat dissipation properties. The packaged frame is made of alumina, and the chip is sealed by potting, thereby suppressing cost. It is a package developed for logic LSI that can tolerate W3 power under natural air cooling conditions. A 208-pin (0.5mm center-to-center) and 160-pin (0.65mm center-to-center) LSI logic package has been developed and started mass production in October 1993.

29, MCM (multi-chip module)

Multi-chip components. A package in which a plurality of semiconductor bare chips are assembled on a wiring substrate. According to the substrate material, it can be divided into three categories: MCM-L, MCM-C and MCM-D. MCM-L is an assembly using a conventional glass epoxy multilayer printed substrate. The wiring density is not so high and the cost is low. MCM-C is a component that uses a thick film technology to form a multilayer wiring with ceramic (alumina or glass ceramic) as a substrate, similar to a thick film hybrid IC using a multilayer ceramic substrate. There is no significant difference between the two. The wiring density is higher than MCM-L. MCM-D is a component that uses a thin film technique to form a multilayer wiring using ceramics (alumina or aluminum nitride) or Si or Al as a substrate. The wiring scheme is the highest among the three components, but the cost is also high.

30, MFP (mini flat package)

Small flat package. Another name for plastic SOP or SSOP (see SOP and SSOP). The name adopted by some semiconductor manufacturers.

31, MQFP (metric quad flat package)

A classification of QFPs in accordance with JEDEC (United States Joint Electronic Equipment Council) standards. Refers to a standard QFP with a center-to-pin distance of 0.65mm and a body thickness of 3.8mm to 2.0mm (see QFP).

32, MQUA (metal quad)

A QFP package developed by Olin Corporation of the United States. Both the substrate and the cover are made of aluminum and sealed with an adhesive. Power can be tolerated from 2.5W to 2.8W under natural air cooling conditions. Japan Shinko Electric Industrial Co., Ltd. was licensed to start production in 1993.

33, MSP (mini square package)

Another name for QFI (see QFI) is called MSP in the early stages of development. QFI is the name given by the Japan Electromechanical Industry Association.

34, OPMAC (over molded pad array carrier)

Molded resin seals the bump display carrier. The name used by Motorola Corporation of the United States for molded resin sealed BGA (see BGA).

35, P-(plastic)

Indicates the mark of the plastic package. For example, PDIP stands for plastic DIP.

36, PAC (pad array carrier)

Bump display carrier, another name for BGA (see BGA).

37, PCLP (printed circuit board leadless package)

Printed circuit boards are leadless packaged. The name adopted by Fujitsu of Japan for plastic QFN (plastic LCC) (see QFN). The pin center distance is 0.55mm and 0.4mm. Currently in the development stage.

38, PFPF (plastic flat package)

Plastic flat package. Another name for plastic QFP (see QFP). The name adopted by some LSI manufacturers.

39, PGA (pin grid array)

Display pin package. In one of the cartridge type packages, the vertical pins on the bottom surface are arranged in a display. The package substrate basically uses a multilayer ceramic substrate. In the case where the material name is not specifically indicated, most of them are ceramic PGAs for high-speed large-scale logic LSI circuits. higher cost. The lead center distance is usually 2.54mm and the number of pins is from 64 to 447. In order to reduce the cost, the package substrate can be replaced with a glass epoxy printed substrate. There are also 64 to 256-pin plastic PG A. In addition, there is a short lead surface mount PGA (PGA) with a 1.27mm lead pitch. (See surface mount PGA).

40, piggy back

Load package. A ceramic package with a socket, similar to DIP, QFP, QFN. Used to evaluate program confirmation operations when developing devices with microcomputers. For example, plug the EPROM into the socket for debugging. This kind of package is basically a fixed product, which is not very circulated on the market.

41, PLCC (plastic leaded chip carrier)

Plastic chip carrier with leads. One of the surface mount packages. The pins are drawn from the four sides of the package and are T-shaped, which is a plastic product. Texas Instruments, Inc., first used in 64k-bit DRAM and 256k DRAM, is now widely used in circuits such as logic LSIs and DLDs (or logic devices). The center of the pin is 1.27mm and the number of pins is from 18 to 84. The J-shaped pin is not easily deformed and is easier to handle than the QFP, but it is difficult to visually check after soldering.

PLCC is similar to LCC (also known as QFN). In the past, the only difference between the two was that the former used plastic and the latter used ceramic. However, the J-lead package made of ceramic and the leadless package made of plastic (labeled as plastic LCC, PC LP, P-LCC, etc.) have become indistinguishable. To this end, the Japan Electromechanical Industry Association decided in 1988 to refer to the package that leads the J-shaped pin from the four sides as QFJ and the package with the electrode bump on the four sides as QFN (see QFJ and QFN).

42. P-LCC (plastic teadless chip carrier) (plastic leaded chip currier)

Sometimes it is another name for plastic QFJ, sometimes it is another name for QFN (plastic LCC) (see QFJ and QFN). Some LSI manufacturers use PLCC for leaded packages and P-LCC for leadless packages to show the difference.

43, QFH (quad flat high package)

Four-sided, thick, flat package. One type of plastic QFP, in order to prevent the package body from breaking, the QFP body is made thicker (see QFP). The name adopted by some semiconductor manufacturers.

44, QFI (quad flat I-leaded packgac)

Four-sided I-shaped pin flat package. One of the surface mount packages. The pins are led out from the four sides of the package and are I down. Also known as MSP (see MSP). The mounting is soldered to the printed substrate. Since the pins have no protruding portions, the mounting area is smaller than QFP. Hitachi has developed and used this package for video analog ICs. In addition, the PLL IC of Motorola Corporation of Japan also uses this package. The center of the pin is 1.27mm and the number of pins is from 18 to 68.

45, QFJ (quad flat J-leaded package)

Four-sided J-pin flat package. One of the surface mount packages. The pins are led out from the four sides of the package and are J-shaped downward. It is the name stipulated by the Japan Electromechanical Industry Association. The center of the pin is 1.27mm.

The materials are plastic and ceramic. Plastic QFJ is often referred to as PLCC (see PLCC) for use in microcomputers, gate displays, DRAM, ASSP, OTP, etc. The number of pins is from 18 to 84.

Ceramic QFJ is also known as CLCC, JLCC (see CLCC). The package with window is used for UV erase type EPROM and microcomputer chip circuit with EPROM. The number of pins is from 32 to 84.

46, QFN (quad flat non-leaded package)

Four-sided, leadless flat package. One of the surface mount packages. Now more called LCC. QFN is the name given by the Japan Electromechanical Industry Association. The four sides of the package are equipped with electrode contacts. Due to the absence of leads, the placement area is smaller than QFP and the height is lower than QFP.

However, when stress is generated between the printed substrate and the package, no relief can be obtained at the electrode contact. Therefore, the electrode contacts are difficult to make as many pins as the QFP, generally from about 14 to about 100. The materials are ceramic and plastic. When there is an LCC mark, it is basically a ceramic QFN. The center of the electrode contacts is 1.27 mm.

Plastic QFN is a low cost package of glass epoxy printed substrate. In addition to the 1.27mm center distance of the electrode contacts, there are two types of 0.65mm and 0.5mm. This package is also known as plastic LCC, PCLC, P-LCC, and the like.

47, QFP (quad flat package)

Four-sided pin flat package. One of the surface mount packages, the leads are drawn from four sides into a gullwing (L) type. The substrate is available in ceramic, metal and plastic. In terms of quantity, plastic packaging accounts for the vast majority. When no material is specifically indicated, it is mostly plastic QFP. Plastic QFP is the most popular multi-pin LSI package. It is used not only for digital logic LSI circuits such as microprocessors and gate displays, but also for analog LSI circuits such as VTR signal processing and acoustic signal processing. The center distance of the pins is 1.0mm, 0.8mm, 0.65mm, 0.5mm, 0.4mm, 0.3mm and other specifications. The maximum number of pins in the 0.65mm center-to-center specification is 304.

In Japan, QFP with a pin center distance of less than 0.65 mm is called QFP (FP). But now the Japanese electromechanical industry has re-evaluated the QFP's form factor. There is no difference in the center distance of the pins, but it is divided into QFP (2.0mm ~ 3.6mm thick), LQFP (1.4mm thick) and TQFP (1.0mm thick) according to the thickness of the package body.

In addition, some LSI manufacturers refer to QFPs with a 0.5mm lead pitch as shrink-type QFP or SQFP or VQFP. However, some manufacturers also refer to the QFP with a pin center distance of 0.65mm and 0.4mm as SQFP, which makes the name slightly confused. The disadvantage of QFP is that the pins are easily bent when the center distance of the pins is less than 0.65 mm.

In order to prevent pin deformation, several improved QFP varieties have emerged. BQFP with a tree-finger cushion at the four corners of the package (see BQFP); GQFP with a resin guard ring covering the front end of the pin (see GQFP); set test bumps in the package body and prevent pin deformation The TPQFP can be tested in a dedicated fixture (see TPQFP).

In terms of logic LSI, many development products and high reliability products are packaged in the multilayer ceramic QFP. Products with a minimum center-to-center distance of 0.4mm and a maximum of 348 pins have also been introduced. In addition, glass-sealed ceramic QFPs are also available (see Gerqa d).

48, QFP (FP) (QFP fine pitch)

Small center distance from QFP. The name specified by the Japan Electromechanical Industry Association standard. Refers to a QFP with a center-to-pin distance of 0.55mm, 0.4mm, 0.3mm, etc., less than 0.65mm (see QFP).

49, QIC (quad in-line ceramic package)

Another name for ceramic QFP. The name used by some semiconductor manufacturers (see QFP, Cerquad).

50, QIP (quad in-line plastic package)

Another name for plastic QFP. The name used by some semiconductor manufacturers (see QFP).

51, QTCP (quad tape carrier package)

Four-sided pin on-board package. One of the TCP packages, which form pins on the insulating tape and emerge from the four sides of the package. It is a thin package using TAB technology (see TAB, TCP).

52, QTP (quad tape carrier package)

Four-sided pin on-board package. The name used by the Japan Electromechanical Industry Association for the form factor specified by QTCP in April 1993 (see TCP).

53, QUIL (quad in-line)

Another name for QUIP (see QUIP).

54, QUIP (quad in-line package)

Four-column in-line package. The pins are led out from both sides of the package, and each other is staggered downward into four columns. The center of the lead is 1.27 mm. When the printed circuit board is inserted, the insertion center distance becomes 2.5 mm. Therefore, it can be used for standard printed wiring boards. It is a smaller package than the standard DIP. Nippon Electric Co., Ltd. uses a variety of packages in microcomputer chips for desktop computers and home appliances. The materials are ceramic and plastic. The number of pins is 64.

55, SDIP (shrink dual in-line package)

Shrinkage type DIP. One of the cartridge type packages, the shape is the same as DIP, but the lead center distance (1.778mm) is less than DIP (2.54 mm).

Therefore, this is called. The number of pins is from 14 to 90. Also known as SH-DIP. The materials are ceramic and plastic.

56, SH-DIP (shrink dual in-line package)

Same as SDIP. The name adopted by some semiconductor manufacturers.

57, SIL (single in-line)

Another name for SIP (see SIP). European semiconductor manufacturers use the name SIL.

58. SIMM (single in-line memory module)

Single column memory component. A memory assembly is provided with electrodes only near one side of the printed substrate. Usually refers to the component that is plugged into the socket. The standard SIMM has 30 electrodes with a center-to-center distance of 2.54mm and a 72-electrode with a center-to-center distance of 1.27mm. SIMMs with 1 megabit and 4 megabit DRAM in SOJ package on one or both sides of a printed circuit board have been widely used in personal computers, workstations, and the like. At least 30-40% of the DRAM is assembled in SIMM.

59, SIP (single in-line package)

Single in-line package. The leads are drawn from one side of the package and arranged in a straight line. The package is side-mounted when assembled onto a printed substrate. The lead center distance is usually 2.54mm and the number of pins is from 2 to 23, most of which are custom products. The shape of the package varies. Some packages that have the same shape as ZIP are called SIP.

60, SK-DIP (skinny dual in-line package)

A type of DIP. Refers to a narrow body DIP with a width of 7.62 mm and a center-to-center spacing of 2.54 mm. Often referred to collectively as DIP (see DIP).

61, SL-DIP (slim dual in-line package)

A type of DIP. Refers to a narrow body DIP with a width of 10.16mm and a pin center distance of 2.54mm. Often referred to collectively as DIP.

62, SMD (surface mount devices)

Surface mount devices. Occasionally, some semiconductor manufacturers classify SOPs as SMDs (see SOP).

63, SO (small out-line)

Another name for SOP. Many other semiconductor manufacturers in the world use this nickname. (see SOP).

64, SOI (small out-line I-leaded package)

I-shaped pin small outline package. One of the surface mount packages. The pins are drawn downward from the two sides of the package in an I-shape with a center-to-center distance of 1.27 mm. The placement area is smaller than the SOP. Hitachi uses this package in analog ICs (motor drive ICs). The number of pins is 26.

65, SOIC (small out-line integrated circuit)

Another name for SOP (see SOP). Many semiconductor manufacturers abroad use this name.

66, SOJ (Small Out-Line J-Leaded Package)

J-shaped pin small outline package. One of the surface mount packages. The pin is drawn from both sides of the package and is J-shaped downward, hence the name. Usually plastic products, mostly used in memory LSI circuits such as DRAM and SRAM, but most of them are DRAM. Many DRAM devices packaged in SO J are mounted on SIMM. The center of the pin is 1.27mm and the number of pins is from 20 to 40 (see SIMM).

67, SQL (Small Out-Line L-leaded package)

The name used for the SOP in accordance with the JEDEC (United States Electronic Equipment Engineering Committee) standard (see SOP).

68, SONF (Small Out-Line Non-Fin)

SOP without heat sink. Same as the usual SOP. In order to show the difference between no heat sinks in the power IC package, NF (non-fin) marks have been intentionally added. The name used by some semiconductor manufacturers (see SOP).

69, SOF (small Out-Line package)

Small outline package. One of the surface mount packages, the leads are gull-winged (L-shaped) from both sides of the package. The materials are plastic and ceramic. Also called SOL and DFP.

In addition to being used for memory LSIs, SOPs are also widely used in circuits such as ASSPs that are not too large. SOP is the most popular surface mount package in areas where the input and output terminals do not exceed 10 to 40. The center of the pin is 1.27mm and the number of pins is from 8 to 44.

In addition, SOPs with a pin pitch less than 1.27mm are also referred to as SSOPs; SOPs with an assembly height of less than 1.27mm are also referred to as TSOPs (see SSOP, TSOP). There is also an SOP with a heat sink.

70, SOW (Small Outline Package (Wide-Jype))

Wide body SOP. The name adopted by some semiconductor manufacturers.

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